On-chip test clock validation using a time-to-digital converter in FPGAs

While on-chip delay measurement combining logic BIST with a variable test clock is an effective way to secure field reliability of VLSI/FPGAs, validation of the variable test clock generated on the chip is important to guarantee measurement accuracy. This paper addresses a method of on-chip test clock validation using a TDC (Time-to-Digital Converter) for FPGAs. The proposed method has two operation modes, one is a resolution measurement mode and the other is a phase difference measurement mode. The resolution measurement mode is performed first to check the resolution of the TDC circuit. The phase difference measurement mode checks the timing difference between the original clock and the generated test clock. Evaluation experiments using a real FPGA device shows that the resolution of the proposed clock validation method using a TDC is 50.46 ps. For a variable test clock with resolution of 96.15 ps, it was confirmed that INL (Integral Non-Linearity) of the clock is within 10% and it was inconsistent with a result observed by an oscilloscope.The 3rd International Test Conference in Asia (ITC-Asia 2019), September 3-5, 2019Tokyo Denki University, Tokyo, Japa

The genetic architecture of the human cerebral cortex

The cerebral cortex underlies our complex cognitive capabilities, yet little is known about the specific genetic loci that influence human cortical structure. To identify genetic variants that affect cortical structure, we conducted a genome-wide association meta-analysis of brain magnetic resonance imaging data from 51,665 individuals. We analyzed the surface area and average thickness of the whole cortex and 34 regions with known functional specializations. We identified 199 significant loci and found significant enrichment for loci influencing total surface area within regulatory elements that are active during prenatal cortical development, supporting the radial unit hypothesis. Loci that affect regional surface area cluster near genes in Wnt signaling pathways, which influence progenitor expansion and areal identity. Variation in cortical structure is genetically correlated with cognitive function, Parkinson's disease, insomnia, depression, neuroticism, and attention deficit hyperactivity disorder

Conversion Discriminative Analysis on Mild Cognitive Impairment Using Multiple Cortical Features from MR Images

Neuroimaging measurements derived from magnetic resonance imaging provide important information required for detecting changes related to the progression of mild cognitive impairment (MCI). Cortical features and changes play a crucial role in revealing unique anatomical patterns of brain regions, and further differentiate MCI patients from normal states. Four cortical features, namely, gray matter volume, cortical thickness, surface area, and mean curvature, were explored for discriminative analysis among three groups including the stable MCI (sMCI), the converted MCI (cMCI), and the normal control (NC) groups. In this study, 158 subjects (72 NC, 46 sMCI, and 40 cMCI) were selected from the Alzheimer's Disease Neuroimaging Initiative. A sparse-constrained regression model based on the l2-1-norm was introduced to reduce the feature dimensionality and retrieve essential features for the discrimination of the three groups by using a support vector machine (SVM). An optimized strategy of feature addition based on the weight of each feature was adopted for the SVM classifier in order to achieve the best classification performance. The baseline cortical features combined with the longitudinal measurements for 2 years of follow-up data yielded prominent classification results. In particular, the cortical thickness produced a classification with 98.84% accuracy, 97.5% sensitivity, and 100% specificity for the sMCI–cMCI comparison; 92.37% accuracy, 84.78% sensitivity, and 97.22% specificity for the cMCI–NC comparison; and 93.75% accuracy, 92.5% sensitivity, and 94.44% specificity for the sMCI–NC comparison. The best performances obtained by the SVM classifier using the essential features were 5–40% more than those using all of the retained features. The feasibility of the cortical features for the recognition of anatomical patterns was certified; thus, the proposed method has the potential to improve the clinical diagnosis of sub-types of MCI and predict the risk of its conversion to Alzheimer's disease

Quantitative 18F-AV1451 Brain Tau PET Imaging in Cognitively Normal Older Adults, Mild Cognitive Impairment, and Alzheimer's Disease Patients

Recent developments of tau Positron Emission Tomography (PET) allows assessment of regional neurofibrillary tangles (NFTs) deposition in human brain. Among the tau PET molecular probes, 18F-AV1451 is characterized by high selectivity for pathologic tau aggregates over amyloid plaques, limited non-specific binding in white and gray matter, and confined off-target binding. The objectives of the study are (1) to quantitatively characterize regional brain tau deposition measured by 18F-AV1451 PET in cognitively normal older adults (CN), mild cognitive impairment (MCI), and AD participants; (2) to evaluate the correlations between cerebrospinal fluid (CSF) biomarkers or Mini-Mental State Examination (MMSE) and 18F-AV1451 PET standardized uptake value ratio (SUVR); and (3) to evaluate the partial volume effects on 18F-AV1451 brain uptake.Methods: The study included total 115 participants (CN = 49, MCI = 58, and AD = 8) from the Alzheimer's Disease Neuroimaging Initiative (ADNI). Preprocessed 18F-AV1451 PET images, structural MRIs, and demographic and clinical assessments were downloaded from the ADNI database. A reblurred Van Cittertiteration method was used for voxelwise partial volume correction (PVC) on PET images. Structural MRIs were used for PET spatial normalization and region of interest (ROI) definition in standard space. The parametric images of 18F-AV1451 SUVR relative to cerebellum were calculated. The ROI SUVR measurements from PVC and non-PVC SUVR images were compared. The correlation between ROI 18F-AV1451 SUVR and the measurements of MMSE, CSF total tau (t-tau), and phosphorylated tau (p-tau) were also assessed.Results:18F-AV1451 prominently specific binding was found in the amygdala, entorhinal cortex, parahippocampus, fusiform, posterior cingulate, temporal, parietal, and frontal brain regions. Most regional SUVRs showed significantly higher uptake of 18F-AV1451 in AD than MCI and CN participants. SUVRs of small regions like amygdala, entorhinal cortex and parahippocampus were statistically improved by PVC in all groups (p < 0.01). Although there was an increasing tendency of 18F-AV-1451 SUVRs in MCI group compared with CN group, no significant difference of 18F-AV1451 deposition was found between CN and MCI brains with or without PVC (p > 0.05). Declined MMSE score was observed with increasing 18F-AV1451 binding in amygdala, entorhinal cortex, parahippocampus, and fusiform. CSF p-tau was positively correlated with 18F-AV1451 deposition. PVC improved the results of 18F-AV-1451 tau deposition and correlation studies in small brain regions.Conclusion: The typical deposition of 18F-AV1451 tau PET imaging in AD brain was found in amygdala, entorhinal cortex, fusiform and parahippocampus, and these regions were strongly associated with cognitive impairment and CSF biomarkers. Although more deposition was observed in MCI group, the 18F-AV-1451 PET imaging could not differentiate the MCI patients from CN population. More tau deposition related to decreased MMSE score and increased level of CSF p-tau, especially in ROIs of amygdala, entorhinal cortex and parahippocampus. PVC did improve the results of tau deposition and correlation studies in small brain regions and suggest to be routinely used in 18F-AV1451 tau PET quantification

A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy

[[abstract]]A monolithic Vernier-based time-to-digital converter (TDC) with 37.5 ps time resolution and theoretically unlimited input range has been integrated in TSMC 0.35-mum standard 2P4M CMOS technology. Since the proposed circuit utilizes a single-stage Vernier delay line (VDL) for both coarse and fine measurements, no other interpolation circuit is required. The operation frequencies of the single-stage Vernier delay line are stabilized against process, voltage and temperature (PVT) variations by dual phase-locked loops. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured differential nonlinearity is plusmn0.2 LSB, and the measured integral nonlinearity is plusmn0.35 LSB. The power consumption is 150 mW at 100 k samples/s full conversion speed, and the chip size is as small as 0.222 mm2. All the packaged chips were tested to be fully functional over -40degC to 100degC ambient temperature range and 3.0 V to 3.9 V supply voltage range with extremely low resolution variation

A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching

[[abstract]]low-cost and low-power CMOS time-to-digital converter (TDC) with 50-ps time resolution is proposed in this paper. The reference clock frequency of the TDC is 80 MHz and the input range is theoretically unlimited. Two parallel time interpolators are used to improve the resolution by pulse stretching. In addition to conventional current ratio and capacitor ratio, the duty cycle of the discharging clock is also incorporated to adjust the stretch factor to reduce the power consumption and chip area dramatically. The interpolators are based on analog dual-slope conversion. The time resolution is measured as 50 ps and the integral nonlinearity (INL) error is within plusmn1.1 LSB for input range up to 250ns. The temperature drift of the measured resolution is -15.2% to +13% over a temperature range of -40degC to 80degC, which is significantly smaller than plusmn125% drift over 100degC temperature range in previous work. The voltage drift is 3.8 ps/V or equivalently plusmn3.5% over 3.0-4.0 V supply voltage range. The measured resolution is within 49.8 ps to 52.7 ps for six packaged chips and the chip size is merely 0.5 mmtimes0.45mm as fabricated in the TSMC 0.35-mum CMOS digital process. The power consumption is 0.75mW, enormously reduced from hundreds of milliwatts of the predecessors, at 100 k samples/s and the measurement rate can achieve as high as 150 k samples/

A Time-Domain Sub-Micro Watt Temperature Sensor With Digital Set-Point Programming

[[abstract]]To realize the on-chip temperature monitoring of VLSI circuits, an accurate time-domain low-power CMOS thermostat based on delay lines is proposed. Contrary to the voltage-domain predecessors, the proposed circuit can benefit from the performance enhancement due to the scaling down of fabrication processes. By replacing R-string voltage division and voltage comparator with delay line time division and time comparator, only little static power is consumed. The power consumption and chip size can be reduced substantially. Without any bipolar transistor, the temperature sensor composed of a delay line is utilized to generate the delay time proportional to the measured temperature. Instead of a conventional voltage/current DAC or an external resistor, a succeeding multiplexer (MUX) along with a reference delay line is used to program the set-point. The test chips with mixed-mode design were fabricated in a TSMC CMOS 0.35-mum 2P4M digital process. The chip area is merely 0.4 mm2. The effective resolution is around 0.5degC with a 256-to-1 multiplexer and -40degC ~ 80degC nominal temperature range. The achieved measurement error is within plusmn0.8degC for a total of 20 packaged chips over the temperature operation range of commercial ICs. The power consumption is 0.45 muW per conversion and a measurement rate as high as 1 MHz is feasible when necessary